Test Scheduling for Circuits in Micron to Deep Submicron Technologies

We discuss the test scheduling problem in this paper. We first provide a historical perspective of the original test scheduling formulation that dealt only with resource conflicts, followed by the consideration of power constraint test scheduling. We then move on to the recent formulations which include dealing with thermal constraint. We explain solutions, their limitations and the challenges that remain. With the emergence of on-chip sensors, in future it may be possible to leverage the use of such sensors to arrive at more efficient schedules. The paper explains these new opportunities and suggests research directions. This paper also contains an exhaustive list of references that may help the researchers and practitioners dealing with this problem.